Minimum Wirelength Zero Skew Clock Routing Trees with Buffer Insertion

Zero skew clock routing is an issue of increasing importance in the realm of VLSI design. As a result of the increasing speeds of on-chip clocks, zero skew clock tree construction has become critical for the correct operation of high performance VLSI circuits. In addition, in an effort to both reduce power consumption and the deformation of clock signals at synchronizing elements on a chip, a minimum wirelength characteristic of clock tree networks is highly desirable. In an effort to provide a solution to the current issues dealing with zero skew clock tree construction, we present an efficient two-phase algorithm based on the Elmore delay model, which successfully constructs zero skew clock routing trees with buffer insertion and minimum wirelength. The results of an implementation of this algorithm have been verified to display zero skew characteristics in conformance with the Elmore delay model equations. The first phase of the algorithm is a bottom-up delayed merge embedding (DME) with buffer insertion procedure which enumerates all of the possible zero skew clock trees for consideration in the second phase. In the second phase, a top-down procedure of merged embedding is performed with the objective of minimizing wirelength.